Current art integrated circuit (IC) fabrication techniques involve formation of a plurality of individual IC devices on a single semiconductor substrate, termed a “wafer”. After fabrication is completed, the wafer is scribed to separate the individual IC devices called “dice”. Usually the individual dice are spaced apart from one another on the wafer to accommodate the scribing tool used to cut the wafer. The wafer thus has the appearance of a series of IC dice separated by intersecting lines to accommodate the scribing operation. These lines are commonly referred to as “scribing lanes”. For cost saving purpose, it is desirable to test the dice while they are still in wafer form (called “wafer level testing”). The major difficulty for wafer level testing is the need to establish connections between the tester and the input or output (I/O) signals in each die. Typically, wafer level testing is performed by placing a series of probe needles in contact with bonding pads that are formed on an exposed metal surface of each IC die. These bonding pads are also used to connect elements of a lead frame if the IC die is subsequently packaged. An expensive stepping device moves the probe needles to connect different dice for a tester to test them one by one. Defective dice are marked with ink after they failed such wafer level tests. Unfortunately, individual dice that have passed wafer level tests may still fail in later continuous operation due to reliability problems. A common practice in the IC industry to detect reliability problems is called “burn-in”. During burn-in tests, IC devices are exercised at elevated temperature and elevated power supply voltage. It is known that IC dice pass these burn-in tests are highly reliable in practical operation conditions. Conventional burn-in tests are usually done after the IC dice are packaged because of the difficulty in using probe stepping devices in those harsh burn-in conditions.
It is desirable to avoid using a costly stepping probe tester for wafer level tests. It is even more desirable to do burn-in tests at wafer level. The major obstacle for wafer level testing is the difficulty to transfer data between the tester and the individual dice on a wafer. One method is to use a probing device that provides all necessary connections to all the dice on a wafer. Such probing device would have thousands of probe needles and metal lines. It is not practical to build such complex probing devices. Another approach is to transfer testing data into and out of each die through conductive lines patterned on the wafer. This approach is also very difficult. The insulator materials used to separate conductor layers in IC (called interlayer dielectric) have a strong tendency to absorb water moisture, which is known to cause reliability problems. It is a common practice to cover the wafer with a layer of water-resist thin film. This water-resist layer can be destroyed during wafer scribing so that moisture still can penetrate through the exposed edges of scribed dice. A common solution to this problem is to build a continuous metal wall (called “seal ring”) between internal circuits and scribing lanes. Combination of the seal ring and the water-resist layer provides a complete water-resist shield for scribed dice. In the mean time, the seal ring also becomes a barrier for all conducting layers used in normal IC fabrication procedures. It is therefore necessary to use additional procedures to deposit wafer level connection lines after all normal IC fabrication procedures have been done. One example of such approach was proposed in U.S. Pat. No. 5,053,900 to W. Parrish. This patent describes the formation of multiple conductive lines along the scribing lanes of a wafer after normal IC fabrication processes are done. These conductive lines connect enlarged I/O pads at the edges of the wafer with suitable multiplexing circuitry formed in an otherwise unused circuit of the wafer. The conductive lines connect the I/O pads of the individual IC dice to the multiplexing circuitry. Wafer level testing is then performed by placing a single set of test probes in contact with a set of enlarged I/O pads associated with the multiplexing circuitry. The multiplexing circuitry selectively connects the test probes with the individual IC dice to be tested through the wafer level conductive lines. These conductive lines would be destroyed by the subsequent die scribing processes. Because there are a large amount of metal in the scribing lane, some of the I/O pads of the individual IC dice may be electrically shorted after the scribing process. Slivers of conductive materials may remain in proximity to sensitive regions of the IC dice. These slivers may interfere with subsequent bonding operations by shorting an IC die with unintended conductive bridges between adjacent I/O pads on the die. In U.S. Pat. No. 5,532,174, Corrigan describes a method to solve the problems caused by scribed metal lines. Corrigan provides the wafer level conductive lines using a sacrificial conductive layer that is removed from the wafer by etching before the scribing process. To facilitate its removal, this conductive layer is formed from a conductive material differing from the conductive material employed to form the I/O pads of the IC dice. Another approach is described in U.S. Pat. No. 5,399,505 to Dasse et al. Wafer level connections are formed after normal IC fabrication procedures to connect probe points to the bonding pads of a plurality of IC dice. External probe needles connected to those probe points provide testing connections to test a plurality of dice, while the bonding pads in each die remain ready for subsequent bonding processes. In U.S. Pat. No. 5,593,903 Beckenbaugh et al. describe methods to deposit multiple layers of metals and insulators on semiconductor wafers after normal IC fabrications are done. The wafer conductors are electrically coupled to bonding pads on each of a plurality of IC die on the wafer at a first end and to wafer test pads at the periphery of the wafer at the second end. Thus, the wafer conductors, wafer test pads and contact pads allow each integrated circuit die to be accessed individually for electrical testing. When all the testing conductors are removed after testing, the bonding pads of each IC die are returned to the same condition they had prior to the formation of the testing conductors.
All of the above inventions require additional manufacture procedures to build wafer level connections. These additional procedures increase manufacture cost. They also introduce additional yield loss. These wafer level conductive lines need to connect the bonding pads in all IC dice on a wafer. The most popular wafer size for the current art IC technologies is 8 inches, and the industry is moving into 12-inch wafer. There are thousands of dice in each current art wafer. The wafer level connections will need to use thousands of 8-inch or 12-inch long lines to connect all dice on each wafer. These conductive lines occupy a large area on the wafer. It is therefore likely to cause additional yield loss at subsequent scribing process. The etching processes to remove testing conductor lines are equally likely to cause additional yield loss. Due to the resistance-capacitance propagation delays (RC delays) of those large area testing lines, it is very difficult to do high frequency tests using such large area conductive lines. All of those inventions provide testing methods to test one die at a time. Those inventions provide little improvement in testing time while testing time is usually the dominating factor that defines testing cost. All the above methods are useful only for wafer level tests or burn-in tests; they are not supporting the actual applications of the IC products.
It is therefore highly desirable to provide wafer level data transfer methods using a small number of small area conductive lines. It is also desirable to support parallel testing so that a large number of dice can be tested simultaneously. Testing time, and therefore testing cost, can be reduced significantly. The wafer level data transfer methods are not only useful for testing purpose. It is even more desirable to provide extremely powerful parallel processing IC products using wafer level connections.
For current art IC manufacture, a completed wafer is scribed to separate the individual IC. Each separated die is packaged for further integration with other IC and circuit elements. A packaged IC is called a “chip”. Multiple chips are mounted on printed circuit boards (PCB) for electrical connections. Multiple PCB modules are mounted into a box to form the final product. Each assembly stage (IC→Chip→PCB→box) adds additional cost and increases occupied space. Each stage involves wide varieties of complex technologies that may cause yield losses. Each stage also adds additional loading to electrical connections that degrade performance and/or increase power consumption. It is therefore highly desirable to integrate as many circuits as possible into individual IC to reduce chip counts on modules. One classic example for chip count reduction is the “chip set” used in personal computer (PC). In the past decade, IC industry has been trying to integrate as many circuits as possible into IC chips as a method to reduce cost, volume, and power for electronic products. When more circuits are integrated into one IC, the IC will have larger die size. However, the die size can not be increased without limitation. The chance to have manufacture defects in a die increases rapidly with increasing die size. Therefore, the cost of IC also increases rapidly with die size due to area related yield loss. This die size limitation is therefore the major limitation on the amount of circuits that can be integrated into an individual IC. It is highly desirable to provide methods to break this die-size barrier to achieve high integration for IC products.